<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>HSTR_EL2</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">HSTR_EL2, Hypervisor System Trap Register</h1><p>The HSTR_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>Controls trapping to EL2 of EL1 or lower AArch32 accesses to the System register in the coproc == <span class="binarynumber">0b1111</span> encoding space, by the CRn value used to access the register using MCR or MRC instruction. When the register is accessible using an MCRR or MRRC instruction, this is the CRm value used to access the register.</p>
      <h2>Configuration</h2><p>AArch64 System register HSTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-hstr.html">HSTR[31:0]</a>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>

      
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>HSTR_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When AArch32 is supported:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_16">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="16"><a href="#fieldset_0-63_16">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">T15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-13_13">T13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-12_12">T12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-11_11">T11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-10_10">T10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-9_9">T9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-8_8">T8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-7_7">T7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-6_6">T6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-5_5">T5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-3_3">T3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-2_2">T2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-1_1">T1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_0-0_0">T0</a></td></tr></tbody></table><h4 id="fieldset_0-63_16">Bits [63:16, 14, 4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15">T&lt;n&gt;, bit [n], for n = 15, 13 to 5, 3 to 0</h4><div class="field"><p>The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == <span class="binarynumber">0b1111</span> encoding space, are trapped to EL2 as follows:</p>
<ul>
<li>MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value <span class="hexnumber">0x03</span>, unless the access is <span class="arm-defined-word">UNDEFINED</span>.
</li><li>MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value <span class="hexnumber">0x04</span>, unless the access is <span class="arm-defined-word">UNDEFINED</span>.
</li></ul><table class="valuetable"><tr><th>T&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control has no effect on EL0 or EL1 accesses to System registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>System registers in the coproc == <span class="binarynumber">0b1111</span> encoding space and CRn == &lt;n&gt; or CRm == &lt;n&gt; where T&lt;n&gt; is the name of this field, are trapped as follows:</p>
<ul>
<li>
<p>An EL1 MCR or MRC access is trapped to EL2.</p>

</li><li>
<p>An EL0 MCR or MRC access is trapped to EL2, if the access is not <span class="arm-defined-word">UNDEFINED</span> when the value of this field is 0.</p>

</li><li>
<p>An EL1 MCRR or MRRC access is trapped to EL2.</p>

</li><li>
<p>An EL0 MCRR or MRRC access is trapped to EL2, if the access is not <span class="arm-defined-word">UNDEFINED</span> when the value of this field is 0.</p>

</li></ul>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether an EL0 access using AArch32 is trapped to EL2, or is <span class="arm-defined-word">UNDEFINED</span>.</p>
<p>If the access is <span class="arm-defined-word">UNDEFINED</span>, and generates an exception that is taken to EL1 or EL2 using AArch64, this is reported with EC syndrome value <span class="hexnumber">0x00</span>.</p>
<div class="note"><span class="note-header">Note</span><p>Arm expects that trapping to EL2 of EL0 accesses to these registers is unusual and used only when the hypervisor must virtualize EL0 operation. Arm recommends that, whenever possible, EL0 accesses to these registers behave as they would if the implementation did not include EL2. This means that, if the architecture does not support the EL0 access, then the register access instruction is treated as <span class="arm-defined-word">UNDEFINED</span> and generates an exception that is taken to EL1.</p></div></td></tr></table><p>For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1:</p>
<ul>
<li>An MCR or MRC instruction with coproc set to <span class="binarynumber">0b1111</span> and &lt;CRn&gt; set to c7 is trapped to EL2.
</li><li>An MCRR or MRRC instruction with coproc set to <span class="binarynumber">0b1111</span> and &lt;CRm&gt; set to c7 is trapped to EL2.
</li></ul>
<p>When <span class="xref">FEAT_VHE</span> is implemented, and the value of <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_1-63_0">Bits [63:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing HSTR_EL2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, HSTR_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        X[t, 64] = NVMem[0x080];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    X[t, 64] = HSTR_EL2;
elsif PSTATE.EL == EL3 then
    X[t, 64] = HSTR_EL2;
                </p><h4 class="assembler">MSR HSTR_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        NVMem[0x080] = X[t, 64];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    HSTR_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    HSTR_EL2 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
